1. Field of the Invention
This invention generally relates to intrasystem connections of electrical computers, and more particularly to an interface architecture for a bus bridge between busses of different data widths.
2. Description of the Related Art
When a Digital Signal Processor (DSP) is the only processor of a computer system such as a System-on-Chip, the DSP must perform both control and signal processing functions. As part of its control function, a 16-bit DSP is required, at times, to perform write accesses to a 32-bit input/output device, or peripheral, that only allows 32-bit write accesses. The 16-bit DSP is coupled to the 32-bit-only peripheral by a bridge. In a conventional programming model, DSP firmware or software is required to perform two entire 16-bit write operations to the peripheral in order to correctly write control data to the 32-bit-only peripheral. Meeting this requirement disadvantageously increases software overhead and reduces the performance of the DSP when executing application code to the peripheral.
Such known conventional write accesses are accomplished by the DSP firmware or software performing the sequence of a) read, b) modify and c) write. Disadvantageously, all known methods require an N-bit DSP to perform the foregoing sequence twice, which, for a two-cycle access DSP, totals to two read cycles and two write cycles, in order to modify the data at a single 2N-bit location of a peripheral. The resulting write access to the peripheral using prior art techniques is inefficient with respect to processor task management, in that a single write access requires four (4) DSP instructions of reading or writing. Using known methods and apparatus, each occasion that the 16-bit, two-cycle access DSP writes to the 32-bit-only peripheral disadvantageously uses at least eight (8) clock cycles of the DSP.
For example, assume a computer system includes a two-cycle access 16-bit DSP and a 32-bit-only peripheral, and that it is pre-determined that a data location having DSP address “0” coincides with a low sixteen (16) bits of a 32-bit data location of the 32-bit-only peripheral and that a data location having DSP address “1” coincides with a high sixteen (16) bits of the 32-bit data location of the 32-bit-only peripheral. If the 16-bit DSP writes to the 32-bit-only peripheral in order to modify the high sixteen (16) bits of the 32-bit data location, such as at peripheral address “1”, the following disadvantageously large number of operations would be needed: a) the DSP performs a 16-bit read at address “0”; however, such read data is not returned to the DSP until the bridge completes the next operation, which stalls the DSP, thereby effectively adding additional clock cycles to the at least eight (8) clock cycles of the DSP time; b) a 32-bit read from the peripheral is performed by the bridge at address “0” of the 32-bit-only peripheral; c) the DSP performs a 16-bit read at address “1”; d) within the internal registers of the DSP, the contents of the 16-bit word at address “1” is modified; e) the DSP performs a 16-bit write at address “0”; f) the DSP performs a 16-bit write at address “1”; and g) a 32-bit write at address “0” is performed by the bridge on the 32-bit-only peripheral.
In the case of the 16-bit DSP modifying sixteen (16) bits of a 32-bit register, a total of six (6) operations are needed, two (2) DSP reads, two (2) DSP writes, one (1) bridge read and one (1) bridge write. Each read operation of the DSP requires a number of clock cycles that depends upon a ratio between a speed of a clock for a DSP bus and a usually slower speed of a clock for a peripheral bus. Each write operation of the DSP is executed at the speed of the DSP bus because data is usually written to a temporary buffer on the bridge.